1. Field of the Invention
The invention relates in general to an electro-luminescent (EL) display panel, and more particularly to an EL display panel with Digital-Analogy Converter (DAC).
2. Description of the Related Art
The light emitting luminance of a light emitting diode (LED) pixel is directly proportional to the current flowing through the pixel, so the pixel is usually driven by the current. The LED pixel generates the corresponding luminance according to the pixel currents, which are provided by the drive circuit according to different grey levels. So, the magnitude of the pixel current directly influences the light emitting luminance of the LED pixel. There are many methods for generating the pixel current. Most of the methods utilize the TFT as the current source, set N current sources according to 2N grey levels, and generate N current values, which are (20)I, (21)I, (22)I, . . . (2N-1)I, wherein N is a positive integer. During the display process, the corresponding current sources are turned on according to the grey levels, and the currents supplied by the current sources that are turned on are summated and then outputted as the pixel current.
FIG. 1 is a schematic illustration showing the circuit architecture of a conventional DAC. For example, a DAC 100 for generating eight pixel currents IP includes nine TFTs QA1 to QA3, QB1 to QB3 and QC1 to QC3. The TFTs QA1 to QA3 serving as current sources have ratios (W/L, 2W/L and 4W/L) of channel widths to channel lengths so as to generate currents I, 2I and 4I with different magnitudes.
It is assumed that when the grey level D is data signals (D2 D1 D0)=(110)2, the TFT QB1 is turned off, the current I flows through the TFTs QC1 and QA1 to the ground, and the TFTs QB2 and QB3 are turned on because the data signals D2 and D1 are high. Thus, the currents 2I and 4I serving as the pixel current IP flow through the TFTs QB2, QB3 and QA2, QA3 to the ground, respectively. Hence, the pixel current IP supplied by the DAC 100 is 2I+4I=6I, which is outputted to the corresponding pixel to display the luminance represented by the grey level D=(110)2.
However, the present DAC 100 is usually formed using the low-temperature polysilicon manufacturing processes such that the DAC can be integrated into the display panel of the LED display. The current sources are implemented by the low-temperature polysilicon TFTs QA1 to QA3, or by the circuit composed of the TFTs serving as the architecture. Regardless of the architecture, the TFT manufactured using the low-temperature polysilicon technology may have differences in the threshold voltage variation and the carrier mobility variation owing to the laser crystallization process. Thus, the TFTs such as QA1 to QA3 serving as the current sources may have different threshold voltage variations and carrier mobility variations, the pixel current IP supplied by the DAC 100 differs from the current corresponding to the grey level D, and the predetermined light emitting luminance cannot be reached accordingly.
FIG. 2 is a schematic illustration showing the distribution of the conventional current sources. The conventional solution is to evenly distribute the current sources that generate the currents I, 2I, 4I and 8I. That is, each current source ideally generates a constant current I. For example, two current sources are used to generate the current of 2I, four current sources are used to generate the current of 4I, and eight current sources are used to generate the current of 8I, and so on. The even distribution in the space for reducing the difference between the pixel currents IP will be described in the following. As shown in FIG. 2, the eight current sources are used to generate the current of 8I when the pixel current IP corresponding to the grey level D is 8I, wherein the eight current sources A, B, C, D, E, F, G and H are respectively disposed at the right and left sides. This method, however, greatly enlarges the area of the DAC 100. Thus, it is an important subject of the industry to solve the problem of the uneven frames due to the laser crystallization process, which causes the different threshold voltage variations and carrier mobility variations in the TFTs.